Call for Participation – 26th International Conference on Parallel Architectures and Compilation Techniques (PACT 2017)

 

https://parasol.tamu.edu/pact17/

Sept 9-13th, 2017

Portland, Oregon

 

The purpose of PACT 2017 is to bring together researchers
from architecture, compilers, applications and languages to present and discuss
innovative research of common interest. We invite attendees to register for our
exciting program this year consisting of many informative workshops/tutorials,
leading industry keynotes and conference papers and posters.

 

Important Dates:

– August 14th, 2017: Early Registration Deadline

– August 21st, 2017: Student Travel Grants Deadline

– Sept 9-13th, 2017: Conference

 

PACT 2017 Preliminary Program

Workshop/Tutorial Schedule 

Saturday, Sept 9th          

 Time
Workshop/Tutorial Name

AM
AVX-512: AVX-512 Architecture Insights, Compiler Optimizations and Code
Modernization

 

AM
AMD’s Radeon Open Compute and Heterogeneous System Architecture, an open
standard foundation for deep learning and highly scalable compute

 

AM+PM       ANDARE: Workshop on Autotuning and Adaptivity Approaches for Energy Efficient HPC

 

AM+PM       Parallelism in Computer Arithmetic: From Circuits to GPU-Based Supercomputers

 

PM
rCUDA: Boosting the performance of hybrid CPU-GPU clusters with rCUDA

 

PM
Min-Move 2017: Hardware/Software Techniques for Minimizing Data Movement

 

Sunday, Sept 10th             

 

Time
Name Workshop/Tutorial

 

AM
CISC 2017: Computational Intelligence & Soft Computing

 

AM+PM        AIM:
Workshop on Architectures for Intelligent Machines

 

AM+PM        HARP:
Intel Hardware Accelerator Research Program – A Tutorial for learning and using
the Intel Xeon with integrated FPGA

 

AM+PM        OmpSs:
Heterogeneous Parallel Programming with OmpSs

 

PM
DFM 2017: Data Flow Models for Extreme-Scale Computing

 

Main conference

 

Day 1 — Monday, Sept 11th

 

7:00-8:00
Registration & Breakfast

 

8:00-8:30
Opening

 

8:30-9:30
Keynote: Marc Tremblay, Microsoft: “Cloud Performance – AI and Others”

 

9:30-10:00
Break

 

10:00-11:40
Session 1:  Algorithms and data structures

  • RCU-HTM: Combining RCU with HTM to Implement Highly Efficient Concurrent Binary Search Trees. Dimitrios Siakavaras, Konstantinos Nikas, Georgios Goumas, and Nectarios Koziris (National Technical University of Athens)
  • Redesigning Go’s Built-In Map to Support Concurrent Operations. Louis Jenkins (Bloomsburg University), Tingzhe Zhou (Lehigh University), and Michael Spear (Lehigh University)
  • MultiGraph: Efficient Graph Processing on GPUs. Changwan Hong, Aravind Sukumaran-Rajam, Jinsung Kim, P. Sadayappan (The Ohio State University)
  • An Ultra Low-power Hardware Accelerator for Acoustic Scoring in Speech
    Recognition. Hamid Tabani, Jose Maria Arnau, Jordi Tubella, and Antonio Gonzalez (Universitat Politècnica de Catalunya)

11:40-1:10
Lunch

 

  • 1:10-2:50
    Session 2: Approximate and speculative computations

    DrMP: Mixed Precision-aware DRAM for High Performance Approximate and Precise Computing. Xianwei Zhang, Youtao Zhang, Bruce R. Childers, and Jun Yang (University of Pittsburgh)
  • SAM: Optimizing Multithreaded Cores for Speculative Parallelism. Maleen
    Abeydeera, Suvinay Subramanian, Mark C. Jeffrey (MIT), Joel Emer (MIT/Nvidia), and Daniel Sanchez (MIT)
  • Performance Improvement via Always-Abort HTM. Joseph Izraelevitz (University of Rochester), Lingxiang Xiang (Intel Corporation), and Michael L. Scott (University of Rochester)
  • DRUT: An Efficient Turbo Boost Solution via Load Balancing in Decoupled Look-ahead Architecture. Raj Parihar (Cadence Design Systems), and Michael C. Huang (University of Rochester)

 

2:50-3:20
Break

 

3:20-4:10
Session 3: Data & Emerging Use Cases

  • Proxy Benchmarks for Emerging Big-data Workloads. Reena Panda, and Lizy Kurian John (University of Texas at Austin)
  • Lightweight Provenance Service for High Performance Computing. Dong Dai, Yong Chen (Texas Tech University), Philip Carns, John Jenkins, and Robert Ross (Argonne National Laboratory)

 

4:10-5:00
Poster presentations

 

6:00-8:00pm       Reception + Poster Session

 

Day 2 – Sept 12th, Tuesday

 

7:30-8:30
Registration & Breakfast

 

8:30-9:30
Keynote – P. Sadayappan, Ohio State University: “Can compilers help us achieve high performance, productivity and portability?”

 

9:30-10:00
Break

 

10-11:40
Session 4: Memory 1

  • Nexus: A New Approach to Replication in Distributed Shared Caches. Po-An Tsai (MIT), Nathan Beckmann (CMU), and Daniel Sanchez (MIT)
  • Leeway: Highly Adaptive Cache Management. Priyank Faldu, and Boris Grot
    (University of Edinburgh)
  • Application Clustering Policies to Address System Fairness with Intel’s Cache
    Allocation Technology. Vicent Selfa, Julio Sahuquillo (Universitat Politècnica
    de València), Lieven Eeckhout (UGENT), Salvador Petit, and Maria E. Gómez
    (Universitat Politècnica de València)
  • Transparent Dual Memory Compression Architecture. Seikwon Kim, Seonyoung Lee, Taehoon Kim, and Jaehyuk Huh (KAIST)

 

11:40-1:10
Lunch

 

1:10-2:50
Session 5: Best Papers (GPU computing and energy efficiency)

  • End-to-end Deep Learning of Optimization Heuristics. Chris Cummins, Pavlos
    Petoumenos (University of Edinburgh), Zheng Wang (Lancaster University), and Hugh Leather (University of Edinburgh)
  • Graphie: Large-Scale Asynchronous Graph Traversals on Just a GPU. Wei Han, Daniel Edward Mawhirter (Colorado School of Mines), and Matthew Buland (Salesforce)
  • A GPU-Friendly Skiplist Algorithm. Nurit Moscovici (Technion), Nachshon Cohen (EPFL), and Erez Petrank (Technion)
  • A Formal Approach to Minimize Voltage Guardbands under Variation in
    Networks-on-Chip for Energy Efficiency. Raghavendra Pradyumna Pothukuchi (University of Illinois at Urbana Champaign), Amin Ansari (Qualcomm), Bhargava Gopi Reddy, and Josep Torrellas (University of Illinois at Urbana Champaign)

 

2:50-3:20
Break

 

3:20-5:00
Session 6: Memory 2

  • Avoiding TLB Shootdowns through Self-invalidating TLB Entries. Amro Awad
    (Sandia National Laboratories), Arkaprava Basu (AMD Research), Sergey
    Blagodurov (AMD Research), Yan Solihin (North Carolina State University), and Gabriel H. Loh (AMD Research)
  • Weak Memory Models: Balancing Definitional Simplicity and Implementation
    Flexibility. Sizhuo Zhang (MIT), Muralidaran Vijayaraghavan (MIT), and Arvind (MIT)
  • Near-Memory Address Translation. Javier Picorel (EPFL), Djordje Jevdjic
    (University of Washington), and Babak Falsafi (EPFL)
  • Restore-Free In-Place Checkpointing in Non-Volatile Main Memory for Scientific Algorithms. Mohammad Alshboul, Hussein Elnawawy, James Tuck, and  Yan Solihin (North Carolina State University)

 

5:35pm Bus departs from hotel to excursion (cruise)

 

Day 3 – Sept 13th, Wednesday

 

7:30-8:30
Breakfast & Registration

 

8:30-9:30
Keynote: Pradeep Dubey, Intel:  “AI and The Virtuous Cycle of Compute”

 

9:30-10:00
Break

 

10:00-10:50        ACM SRC Presentations

 

10:50-11:05
Break

 

11:05-12:20
Session 7: Translation

  • SuperGraph-SLP Auto-Vectorization. Vasileios Porpodas (Intel Corporation)
  • Exploiting Asymmetric SIMD Register Configurations in ARM-to-x86 Dynamic Binary Translation. Yu-Ping Liu (National Taiwan University), Ding-Yong Hong, Jan-Jan Wu (Academia Sinica), Sheng-Yu Fu, and Wei-Chung Hsu (National Taiwan University)
  • A Generalized Framework for Automatic Scripting Language Parallelization.
    Taewook Oh, Stephen R. Beard, Nick P. Johnson, Sergiy Popovych, and David I. August (Princeton University)

 

12:20-12:35
Best paper & ACM SRC Awards


Conference Close

PACT 2017 Call for Participation — Early Registration Deadline