8th Workshop on Irregular Applications: Architectures and Algorithms
In Conjuction with SC18
Sponsored by IEEE TCHPC
Call for Papers
Irregular applications occur in many subject matters. While inherently parallel, they exhibit highly variable execution performance at a local level due to unpredictable memory access patterns and/or network transfers, divergent control structures, and data imbalances. Moreover, they often require fine-grain synchronization and communication on large-data structures such as graphs, trees, unstructured grids, sparse matrices, deep nets, tables, and their combinations (such as, for example, attributed graphs). They have a significant degree of latent parallelism, which however is difficult to exploit due to their complex behavior. Current high performance architectures rely on data locality and regular computation to reduce access latencies, and often do not cope well with the requirements of these applications. Furthermore, irregular applications are difficult to scale on current supercomputing machines, due to their limits in fine-grained synchronization and small data transfers.
Irregular applications pertain both to well established and emerging fields, such as machine learning, social network analysis, bioinformatics, semantic graph databases, Computer Aided Design (CAD), and computer security. Many of these application areas also process massive sets of unstructured data, which keep growing exponentially. Addressing the issues of irregular applications on current and future architectures will become critical to solve the challenges in science and data analysis of the next few years.
This workshop seeks to explore solutions for supporting efficient execution of irregular applications in the form of new features at the level of the micro- and system-architecture, network, languages and libraries, runtimes, compilers, analysis, algorithms. Topics of interest, of both theoretical and practical significance, include but are not limited to:
– Micro- and System-architectures, including multi- and many-core designs, heterogeneous processors, accelerators (GPUs, vector processors, Automata processor), reconfigurable (coarse grained reconfigurable and FPGA designs) and custom processors
– Network architectures and interconnect (including high-radix networks, optical interconnects)
– Novel memory architectures and designs (including processors-in memory)
– Impact of new computing paradigms on irregular workloads (including neuromorphic processors and quantum computing)
– Modeling, simulation and evaluation of novel architectures with irregular workloads
– Innovative algorithmic techniques
– Combinatorial algorithms (graph algorithms, sparse linear algebra, etc.)
– Impact of irregularity on machine learning approaches
– Parallelization techniques and data structures for irregular workloads
– Data structures combining regular and irregular computations (e.g., attributed graphs)
– Approaches for managing massive unstructured datasets (including streaming data)
– Languages and programming models for irregular workloads
– Library and runtime support for irregular workloads
– Compiler and analysis techniques for irregular workloads
– High performance data analytics applications, including graph databases
Besides regular papers, papers describing work-in-progress or incomplete but sound, innovative ideas related to the workshop theme are also encouraged. We solicit both 8-page regular papers and 4-page position papers. Authors of exciting but not mature enough regular papers may be offered the option of a short 4-page paper and related short presentation.
Abstract Submission: August 22, 2018
Position or Regular Paper Submission: August 29, 2018
Notification: September 28, 2018
Camera-ready: October 10, 2018
Workshop: November 12, 2018
Submission site: https://submissions.supercomputing.org
Submitted manuscripts may not exceed eight (8) pages in length for regular papers and four (4) pages for position papers including figures, tables and references.
Authors of regular papers will be able to provide up to one (1) additional pages for the Artifact Description (AD) appendix and, after paper acceptance, up to two (2) additional pages for the Artifact Evaluation (AE) appendix.
The workshop proceedings will be published through IEEE TCHPC and will be included in the IEEE Xplore digital library.
The templates are available at:
Artifact Description & Evaluation
This edition of the workshop invites authors of regular papers to follow a reproducibility initiative like the main SC Conference, with specific appendices for the Artifact Description (AD) and the Artifact Evaluation (AE). Please refer to the SC reproducibility page for further details on the rationale behind AD and AE: https://sc18.supercomputing.org/submit/sc-reproducibility-initiative/.
Authors of regular papers will be able to use up to one (1) additional page to provide an Artifact Description (AD) Appendix, describing the details of their software environments and computational experiments to the extent that an independent person could replicate their results. This additional page is voluntary, and must focus only on details on software environments and methods to execute the experiments. It should not add details on the proposed technical approaches. If a paper has no computational results, the appendix only needs to mention that computational results are not part of the paper.
Additionally, authors of accepted regular papers will be invited to formally submit their supporting materials to the Artifact Evaluation (AE) process. The process is voluntary, but authors that will participate in the AE will be eligible for the Best Paper Award of the workshop. Supporting materials for the AE include access to the actual software artifact, shared pubblicly (for example, through the CK – Collective Knowledge – https://github.com/ctuning/ck format), and two (2) further additional pages of the paper that details how to reproduce the results of the paper. For details on how to submit supporting materials to the AE process, please refer to: http://ctuning.org/ae/submission.html. Authors participating in the AE will receive an assessment of the artifact, and the related badge on their paper.
For any additional question on the AD and the AE please contact the Artifact Evaluation Chair Flavio Vella at email@example.com.
Antonino Tumeo (PNNL), firstname.lastname@example.org
John Feo (PNNL/NIAC), email@example.com
Vito Giovanni Castellana (PNNL), vitoGiovanni.firstname.lastname@example.org
Marco Minutoli (PNNL and WSU), email@example.com
Artifact Evaluation Chair
Favio Vella (DIVIDITI), firstname.lastname@example.org
Technical Program Committee
Nesreen Ahmed, Intel, US
Kubilay Atasu, IBM Zurich, CH
Scott Beamer, LBNL, US
Sanjukta Bhowmick, University of Nebraska Omaha, US
Erik Boman, SNL, US
David Brooks, Harvard University, US
Aydin Buluc, LBNL, US
Joe Eaton, NVIDIA, US
Rajiv Gupta, UC Riverside, US
Arif Khan, PNNL, US
Farzad Khorasani, Georgia Tech, US
Peter M. Kogge, University of Notre Dame, US
Manoj Kumar, IBM TJ Watson, US
John Leidel, Tactical Computing Labs, US
Kamesh Madduri, Pennsylvania State University, US
Naoya Maruyama, LLNL, US
Miquel Moretó, Barçelona Supercomputing Center, ES
Maxim Naumov, Facebook, US
Fanny Nina-Paravecino, Northeastern University, US
Sreepathi Pai, Rochester University, US
Roger Pearce, LLNL, US
Miquel Pericas, Chalmers University of Technology, SE
Keshav Pingali, University of Texas at Austin, US
Viktor K. Prasanna, University of Southern California, US
Jason Riedy, Georgia Tech, US
John Shalf, LBNL, US
Shaden Smith, Intel, US
Edgar Solomonik, University of Illinois at Urbana-Champaign, US
Bora Uçar, French National Center for Scientific Research, FR
Ruud van der Pas, Oracle, NL
Ana Lucia Varbanescu, University of Amsterdam, NL
Cheng Wang, Microsoft, US