The 3rd International Workshop on AI-assisted Design for Architecture (AIDArc-3)
in conjunction with ISCA 2020
Valencia, Spain
May 30, 2020
Given the success of AIDArc workshops in 2019 and 2018, and the significantly increased interest in utilizing AI to improve computer architecture in past years, we are thrilled to organize the 3rd AIDArc workshop in 2020, held in conjunction with ISCA-47.
Recent advancements in machine learning algorithms, fueled by increased data availability and high-performance computing infrastructure, have led to successful applications of machine learning (and AI in general) in numerous disciplines and domains. Although much attention has been drawn in the computer architecture community on accelerating machine learning, limited research has been conducted to utilize the power of AI/ML to help architects design better computer architectures and systems.
The AIDArc Workshop is intended to bring together researchers, scientists and practitioners across academia and industry, to share early discoveries, successful examples, and opinions on opportunities and challenges regarding utilizing AI to assist computer architecture designs. Research along this line may potentially transform the way computers are designed and optimized. It may also lead to interesting “self-evolving architecture”, where AI helps to speed up computers which, in turn, are used to speed up the AI.
Topics of submitted papers include, but not limited to, the exploration of artificial intelligence in assisting the design and optimization of:
– Various components of computer system architecture, e.g., branch predictor, cache, memory, I/O, interconnection networks, etc.
– Various design objectives of computer system architecture, e.g., power/energy, performance, resource, reliability, security, etc.
– Different types of computer architectures and systems, e.g., embedded/mobile/wearable devices, CPUs, GPUs, special-purpose accelerators, datacenters, HPCs, etc.
– Interaction of computer architecture with other layers, e.g., operating systems, compilers, circuit-level designs, etc.
Papers of up to 6 pages will be reviewed based on originality, novelty, technical strength, presentation quality, correctness and relevance to the workshop scope. Early but novel works on related topics are highly encouraged. Detailed submission instructions are available at the workshop https://eecs.oregonstate.edu/aidarc/
IMPORTANT DATES
Paper submission due: May 2, 2020
Notification of acceptance: May 9, 2020
Camera-ready papers due: May 23, 2020
Workshop’s date: May 30, 2020
Organizers
Lizhong Chen, Oregon State University