13th IEEE/ACM International Symposium on Networks-on-Chip
October 17 – 18, 2019, New York, USA (Co-located with Embedded Systems Week 2019)
The International Symposium on Networks-on-Chip (NOCS) is the premier event dedicated to interdisciplinary research on on-chip, package-scale, chip-to-chip, and datacenter rack-scale communication technology, architecture, design methods, applications and systems. NOCS brings together scientists and engineers working on network-on-chip (NoC) innovations and applications from inter-related research communities, including discrete optimization and algorithms, computer architecture, networking, circuits and systems, packaging, embedded systems, and design automation. Topics of interest include, but are not limited to:
## NoC Architecture and Implementation
– Network architecture (topology, routing, arbitration)
– Timing, synchronous/asynchronous communication
– NoC reliability issues and solutions
– Security issues and solutions in NoC architectures
– Power/thermal issues at NoC un-core and system-level
– Network interface issues and solutions
– Signaling and circuit design for NoC links and routers
## Communication Analysis, Optimization, & Verification
– NoC performance analysis and Quality of Service
– Modeling, simulation, and synthesis of NoC
– Verification, debug and test of NoC
– NoC design and simulation methodologies and tools
– Benchmarks, experiences on NoC-based hardware
– Communication-efficient algorithms
– Communication workload characterization & evaluation
## Novel NoC Technologies
– Optical, wireless, CNT, and other emerging technologies
– NoC for 2.5D and 3D packages
– Package-specific NoC design
– Network coding and compression solutions
– Approximate computing for NoC and NoC-based systems
## NoC for Intelligent Physical Systems
– NoC design for Deep Learning
– Mapping of existing and emerging applications onto NoC
– NoC case studies, application-specific NoC design
– NoC for FPGA, structured ASIC, CMP and MPSoC
– NoC designs for heterogeneous systems
– NoC for CPU-GPU and data-center-on-a-chip (DCoC)
– Scalable modeling of NoC
– Machine learning for NoC and NoC-based Systems
## NoC at the Un-Core and System-level
– Design of memory subsystem (un-core) including memory controllers, caches, cache coherence protocols in NoC
– NoC for new memory/storage technologies
– NoC support for processing-in-memory
– OS support for NoC
– Programming models for NoCs
– Interactions between large-scale systems (datacenter, edge and fog computing) and NoC-based building blocks
## Inter/Intra-Chip and Rack-Scale Network
– Unified inter/intra-chip networks
– Hybrid chip-scale and datacenter rack-scale networks
– All aspects of inter-chip and rack-scale network design
Electronic paper submission requires a full paper, up to 8 double-column ACM (sigconf) format pages, including figures and references. The program committee will use a double-blind review process to evaluate papers based on scientific merit, innovation, relevance, and presentation. Submitted papers must describe original work that has not been published before or is under review by another conference or journal at the same time. Each submission will be checked for any significant similarity to previously published works or for simultaneous submission to other archival venues, and such papers will be rejected. Proposals for special sessions and demos are invited. Paper submissions and demo proposals by industry researchers or engineers to share their experiences and perspectives are also welcome. A percentage of accepted papers will be recommended for publication in an IEEE journal after revision according to the reviewers’ comments. Please find the detailed submission instructions for paper submission, special session, and demo proposals at the submission webpage.
Important Dates (Anywhere on Earth)
Abstract registration: May 10, 2019
Full paper submission: May 17, 2019
Notification of acceptance: July 8, 2019
Final version due: July 22, 2019
General Chairs
Paul Bogdan (University of Southern California)
Cristina Silvano (Politecnico di Milano)
Technical Program Chairs
Sudeep Pasricha (Colorado State University)
Ajay Joshi (Boston University)
Publicity Chairs
Mario Casu, Politecnico di Torino
Ryan Kim, Colorado State University
Smruti Sarangi, IIT Delhi
Web Chair
Ishan Thakkar, University of Kentucky
Publication Chair
Akram Ben Ahmed (Keio University)
Local Arrangements Chair
Christian Pilato (Politecnico di Milano)
Steering Committee Chair
Radu Marculescu (Carnegie Mellon University)