IWLS 2025 Call for Papers
Workshop website: www.iwls.org
The 34th International Workshop on Logic & Synthesis (IWLS 2025)
June 12–13, 2025, University of Verona, Verona, Italy
The International Workshop on Logic and Synthesis is the premier forum for research in synthesis, optimization, and verification of integrated circuits and systems. Research on logic synthesis for emerging technologies and for novel computing platforms, such as nanoscale systems and biological systems, is also strongly encouraged. The workshop encourages the early dissemination of ideas and results. The workshop accepts complete papers highlighting important new problems in the early stages of development, without providing complete solutions. The emphasis is on novelty and intellectual rigor.
Topics of interest include but are not limited to: hardware synthesis and optimization; software synthesis; hardware/software co-synthesis; power and timing analysis; testing, validation, and verification; synthesis for reconfigurable architectures; hardware compilation for domain-specific languages; and design experiences. Submissions on modeling, analysis, and synthesis for emerging technologies and platforms are particularly encouraged.
The workshop format includes paper presentations, invited talks, social lunch and dinner gatherings, and recreational activities.
Important Dates:
Paper abstract submission deadline: March 21, 2025 (AoE)
Full paper submission deadline: March 28, 2025 (AoE)
Notification of acceptance: May 3, 2025
Final version due: May 30, 2025
Submission site: The link to the submission site will appear on the workshop website soon.
IWLS 2025 Programming Contest:
The details of the IWLS 2025 programming contest will appear on the workshop website soon.
Organizing Committee:
General Chair: Valentina Ciriani, University of Milan
Program Committee Chairs: Walter Lau Neto / Weikang Qian, Synopsys / Shanghai Jiao Tong University
Program Contest Chairs: Alan Mishchenko / Alessandro Tempia Calvino, UC Berkeley / EPFL
Special Session Chair: Tiziano Villa, University of Verona
Finance Chair: Lana Josipović, ETH Zurich
Proceedings Chair: Anna Bernasconi, University of Pisa
Publicity Chairs: Petr Fišer / Jiahui Xu, CTU in Prague / ETH Zurich
Technical Program Committee (Tentative):
Luca Amarù, Synopsys
Anna Bernasconi, University of Pisa
Lei Chen, Huawei Noah’s Ark Lab
Zhufei Chu, Ningbo University
Valentina Ciriani, University of Milan
Fabrizio Ferrandi, Politecnico di Milano
Petr Fišer, CTU in Prague
Aman Gayasen, AMD
Winston Haaswijk, Cadence Design Systems
Jie-Hong Roland Jiang, National Taiwan University
Attila Jurecska, Siemens EDA
Victor Kravets, IBM
Walter Lau Neto, Synopsys
Chang Meng, EPFL
Giulia Meuli, Synopsys
Shin-ichi Minato, Kyoto University
Alan Mishchenko, UC Berkeley
Augusto Neutzling, Real Intent
Stefan Nikolić, University of Novi Sad
Weikang Qian, Shanghai Jiao Tong University
Stefano Quer, Politecnico di Torino
Andre Reis, UFRGS
Tsutomu Sasao, Meiji University
Herman Schmit, Google
Eleonora Testa, Synopsys
Gabriella Trucco, University of Milan
Tiziano Villa, University of Verona
Robert Wille, TU Munich & SCCH GmbH
Cunxi Yu, University of Maryland
Mingfei Yu, EPFL