HPCA 2002
HPCA 2003
HPCA 2004
HPCA 2005
HPCA 2006
HPCA 2002
| Article Title |
Power Issues Related to Branch Prediction |
| Authors |
Dharmesh Parikh; Kevin Skadron; Yan Zhang; Marco Barcella; Mircea R. Stan |
| Article Title |
Control-Theoretic Techniques and Thermal-RC Modeling for Accurate and Localized Dynamic Thermal Management |
| Authors |
Kevin Skadron; Tarek Abdelzaher; Mircea R. Stan |
| Article Title |
A New Memory Monitoring Scheme for Memory-Aware Scheduling and Partitioning |
| Authors |
G.Edward Suh; Srinivas Devadas; Larry Rudolph |
| Article Title |
Using Complete Machine Simulation for Software Power Estimation: The SoftWatt Approach |
| Authors |
Sudhanva Gurumurthi; Anand Sivasubramaniam; Mary Jane Irwin; N. Vijaykrishnan; Mahmut Kandemir; Tao Li; Lizy Kurian John |
| Article Title |
Loose Loops Sink Chips |
| Authors |
Eric Borch; Srilatha Manne; Joel Emer; Eric Tune |
| Article Title |
Exploiting Choice in Resizable Cache Design to Optimize Deep-Submicron Processor Energy-Delay |
| Authors |
Se-Hyun Yang; Babak Falsafi; Michael D. Powell; T. N. Vijaykumar |
| Article Title |
Improving Value Communication for Thread-Level Speculation |
| Authors |
J. Gregory Steffan; Christopher B. Colohan; Antonia Zhai; Todd C. Mowry |
| Article Title |
Thread-Spawning Schemes for Speculative Multithreading |
| Authors |
Pedro Marcuello; Antonio González |
| Article Title |
Eliminating Squashes Through Learning Cross-Thread Violations in Speculative Parallelization for Multiprocessors |
| Authors |
Marcelo Cintra; Josep Torrellas |
| Article Title |
Microarchitectural Simulation and Control of di/dt-induced Power Supply Voltage Variation |
| Authors |
Ed Grochowski; Dave Ayers; Vivek Tiwari |
| Article Title |
Let’s Study Whole-Program Cache Behaviour Analytically |
| Authors |
Xavier Vera; Jingling Xue |
HPCA 2003
| Article Title |
Variability in Architectural Simulations of Multi-Threaded Workloads |
| Authors |
Alaa R. Alameldeen; David A. Wood |
| Article Title |
Front-End Policies for Improved Issue Efficiency in SMT Processors |
| Authors |
Ali El-Moursy; David H. Albonesi |
| Article Title |
Control Techniques to Eliminate Voltage Emergencies in High Performance Processors |
| Authors |
Russ Joseph; David M. Brooks; Margaret Martonosi |
| Article Title |
Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks |
| Authors |
Li Shang, Li-Shiuan Peh; Niraj K. Jha |
| Article Title |
Deterministic Clock Gating for Microprocessor Power Reduction. |
| Authors |
Hai Li; Swarup Bhunia; Yiran Chen; T. N. Vijaykumar; Kaushik Roy |
| Article Title |
A Statistically Rigorous Approach for Improving Simulation Methodology |
| Authors |
Joshua J. Yi; David J. Lilja; Douglas M. Hawkins |
| Article Title |
Caches and Hash Trees for Efficient Memory Integrity Verification |
| Authors |
Blaise Gassend; G. Edward Suh; Dwaine E. Clarke; Marten van Dijk; Srinivas Devadas |
| Article Title |
TCP: Tag Correlating Prefetchers. |
| Authors |
Zhigang Hu; Margaret Martonosi; Stefanos Kaxiras |
| Article Title |
Scalar Operand Networks: On-Chip Interconnect for ILP in Partitioned Architecture |
| Authors |
Michael Bedford Taylor; Walter Lee; Saman P. Amarasinghe; Anant Agarwal |
| Article Title |
Cost-Sensitive Cache Replacement Algorithms |
| Authors |
Jaeheon Jeong; Michel Dubois |
HPCA 2004
| Article Title |
Accurate and Complexity-Effective Spatial Pattern Prediction |
| Authors |
Chi F. Chen; Se-Hyun Yang; Babak Falsafi; Andreas Moshovos |
| Article Title |
Out-of-Order Commit Processors |
| Authors |
Adrián Cristal; Daniel Ortega; Josep Llosa; Mateo Valero |
| Article Title |
Using Prime Numbers for Cache Indexing to Eliminate Conflict Misses |
| Authors |
Mazen Kharbutli; Keith Irwin; Yan Solihin; Jaejin Lee |
| Article Title |
The Thrifty Barrier – Energy-Aware Synchronization in Shared-Memory Multiprocessors |
| Authors |
Jian Li; Jose F. Martinez; Michael C. Huang |
| Article Title |
Organizing the Last Line of Defense before Hitting the Memory Wall for CMP |
| Authors |
Chun Liu; Anand Sivasubramaniam; Mahmut T. Kandemir |
| Article Title |
Architectural Characterization of TCP/IP Packet Processing on the Pentium M Microprocessor |
| Authors |
Srihari Makineni; Ravi R. Iyer |
| Article Title |
Data Cache Prefetching Using a Global History Buffer |
| Authors |
Kyle J. Nesbit; James E. Smith |
| Article Title |
Reducing Energy Consumption of Disk Storage Using Power-Aware Cache Management |
| Authors |
Qingbo Zhu; Francis M. David; Christo Frank Devaraj; Zhenmin Li; Yuanyuan Zhou; Pei Cao |
HPCA 2005
| Article Title |
Unbounded Transactional Memory |
| Authors |
C. Scott Ananian, Krste Asanovic, Bradley C. Kuszmaul, Charles E. Leiserson, Sean Lie |
| Article Title |
A New Scalable and Cost-Effective Congestion Management Strategy for Lossless Multistage Interconnection Networks |
| Authors |
Jose Duato, Ian Johnson, Jose Flich, Finbar Naven, Pedro Javier Garcia, Teresa Nachiondo Frinos |
| Article Title |
A Unified Compressed Memory Hierarchy |
| Authors |
Erik G. Hallnor, Steven K. Reinhardt |
| Article Title |
Power Efficient Processor Architecture and The Cell Processor |
| Authors |
H. Peter Hofstee |
| Article Title |
Checkpointed Early Load Retirement |
| Authors |
Nevin Kirman, Meyrem Kirman, Mainak Chaudhuri, Jose F. Martinez |
| Article Title |
Transition Phase Classification and Prediction |
| Authors |
Jeremy Lau, Stefan Schoenmackers, Brad Calder |
| Article Title |
Performance, Energy, and Thermal Considerations for SMT and CMP Architectures |
| Authors |
Yingmin Li, David M. Brooks, Zhigang Hu, Kevin Skadron |
| Article Title |
Improving Multiple-CMP Systems Using Token Coherence |
| Authors |
Michael R. Marty, Jesse D. Bingham, Mark D. Hill, Alan J. Hu, Milo M. K. Martin, David A. Wood |
| Article Title |
The Soft Error Problem: An Architectural Perspective |
| Authors |
Shubhendu S. Mukherjee, Joel S. Emer, Steven K. Reinhardt |
| Article Title |
SafeMem: Exploiting ECC-Memory for Detecting Memory Leaks and Memory Corruption During Production Runs |
| Authors |
Feng Qin, Shan Lu, Yuanyuan Zhou |
| Article Title |
Chip Multithreading: Opportunities and Challenges |
| Authors |
Lawrence Spracklen, Santosh G. Abraham |
| Article Title |
Voltage and Frequency Control With Adaptive Reaction Time in Multiple-Clock-Domain Processors |
| Authors |
Qiang Wu, Philo Juang, Margaret Martonosi, Douglas W. Clark |
| Article Title |
Characterizing and Comparing Prevailing Simulation Techniques |
| Authors |
Joshua J. Yi, Sreekumar V. Kodakara, Resit Sendag, David J. Lilja, Douglas M. Hawkins |
| Article Title |
A Performance Comparison of DRAM Memory System Optimizations for SMT Processors |
| Authors |
Zhichun Zhu, Zhao Zhang |
HPCA 2006
| Article Title |
LogTM: Log-based transactional memory |
| Authors |
Kevin E. Moore, Jayaram Bobba, Michelle J. Moravan, Mark D. Hill, and David A. Wood |
| Article Title |
Dynamic power-performance adaptation of parallel computation on chip multiprocessors |
| Authors |
Li, Jian, and Jose F. Martinez |
| Article Title |
Construction and use of linear regression models for processor performance analysis |
| Authors |
P. J.Joseph, Kapil Vaswani, Matthew J. Thazhuthaveetil |
| Article Title |
Retention-aware placement in DRAM (RAPID): Software methods for quasi-non-volatile DRAM |
| Authors |
Venkatesan, Ravi K., Stephen Herr, and Eric Rotenberg |
| Article Title |
BulletProof: A defect-tolerant CMP switch architecture |
| Authors |
Kypros Constantinides, Stephen Plaza, Jason Blome, Bin Zhang, Valeria Bertacco, Scott Mahlke, Todd Austin, Michael Orshansky |
| Article Title |
Last level cache (llc) performance of data mining workloads on a cmp-a case study of parallel bioinformatics workloads |
| Authors |
Jaleel, Aamer, Matthew Mattina, and Bruce Jacob |
| Article Title |
CMP design space exploration subject to physical constraints |
| Authors |
Yingmin Lee, Benjamin Lee, David Brooks, Zhigang Hu, Kevin Skadron |
| Article Title |
Phase characterization for power: Evaluating control-flow-based and event-counter-based techniques |
| Authors |
Isci, Canturk, and Margaret Martonosi |
| Article Title |
ReViveI/O: Efficient handling of I/O in highly-available rollback-recovery servers |
| Authors |
Jun Nakano, Pablo Montesinos, Kourosh Gharachorloo, and Josep Torrellas |
| Article Title |
CORD: Cost-effective (and nearly overhead-free) order-recording and data race detection |
| Authors |
Milos Prvulovic |
| Article Title |
DMA-aware memory energy management |
| Authors |
Pandey, Vivek and Jiang, Weihang and Zhou, Yuanyuan and Bianchini, Ricardo |
| Article Title |
The common case transactional behavior of multithreaded programs |
| Authors |
Chung, JaeWoong and Chafi, Hassan and Minh, Chi Cao and McDonald, Austen and Carlstrom, Brian and Kozyrakis, Christos and Olukotun, Kunle |
| Article Title |
Exploiting parallelism and structure to accelerate the simulation of chip multi-processors |
| Authors |
Penry, David A and Fay, Daniel and Hodgdon, David and Wells, Ryan and Schelle, Graham and August, David I and Connors, Dan |
