CALL FOR PAPERS
ACM Transactions on Design Automation of Electronic Systems
Special Issue on High-Level Synthesis for FPGA: Next-Generation Technologies and Applications
Guest Editors
Christian Pilato, Politecnico di Milano
Zhenman Fang, Simon Fraser University
Yuko Hara-Azumi, Tokyo Institute of Technology
Jim Hwang, Xilinx, Inc.
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Due to the end of Dennard scaling and Moore’s law, complex hyper-pipelined processors are increasingly replaced by heterogeneous System-on-Chip (SoC) architectures with many specialized components. FPGA devices are becoming common targets for these systems since they allow fast turn-around time, field upgradability, and easy deployment of hardware/software solutions. To cope with the increasing complexity of such systems, designers need to raise the abstraction level from custom design flows to high-level approaches. High-level synthesis (HLS) is a popular method that allows designers to describe the functionality of a component at the software level and automatically generate the corresponding hardware description, reducing the gap between application and hardware designers. Since HLS has been making a great amount of progress and an increasing number of different application domains are pushing designers towards hardware acceleration, HLS is becoming a key enabling technology for FPGA design.
The application landscape for hardware acceleration is rapidly and deeply changing. Modern applications are increasingly based on machine learning that requires access to huge amounts of data to extract valuable knowledge and make accurate predictions. Also, novel technologies like quantum computing are opening novel research questions on how to design accelerators for these systems (including post-quantum cryptography). The combined requirements of modern technologies and applications pose novel challenges and threats for high-level synthesis. For example, side-channel and adversarial attacks are serious threats for security and machine learning applications.
For the full Call for Papers and submission instructions, go to:
https://dl.acm.org/pb-assets/static_journal_pages/todaes/pdf/CfP-SI-TODAES-HLS_v3-1617802255750.pdf
Important Dates
Submissions deadline: 30 June 2021
First-round review decisions: 31 August 2021
Deadline for revision submissions: 15 October 2021
Notification of final decisions: 31 November 2021
Tentative publication: January/February 2022
For questions and further information, please contact the guest editors at:
* Christian Pilato <christian.pilato@polimi.it>
* Zhenman Fang <zhenman@sfu.ca>
* Yuko Hara-Azumi <hara@cad.ict.e.titech.ac.jp>
* Jim Hwang <jhwang@xilinx.com>